1. Technical Field
This invention relates in general to electronic circuits and, more particularly, to a method and apparatus for reducing memory leakage in an electronic circuit.
2. Description of the Related Art
Over the last ten years, the popularity of mobile devices, including wireless telephones and personal digital assistants, has grown dramatically. For many users of mobile devices, power consumption is an extremely important factor, because such devices operate with a relatively small battery. It is desirable to maximize the battery life in these systems, since it is inconvenient to recharge or replace the batteries after short intervals.
One method to reduce power consumption involves placing various components in a low power state during periods where they are not in use. In some cases, a processing device, such as a general purpose processor or digital signal processor (DSP) can be placed in a low power state or completely powered down after storing its internal data to a non-volatile memory or a powered memory. High-speed random access memory (RAM), however, can not be turned off completely and still retain its data; in order to reduce power and retain data, it may be placed in a “data retention mode”. In data retention mode, data in the memory remains intact, but the RAM cannot be accessed. In a typical data retention mode, the supply voltage, VCC, to the memory is reduced to decrease current leakage.
Many processing devices, such as DSPs, have an internal RAM. When updating a DSP architecture to take advantage of an internal RAM memory with a data retention mode, several approaches have been developed to determine time periods in which to place a memory in data retention mode, based on the operation of an associated processing core. Existing solutions are limited to optimization of the power consumption through complex external hardware or through complicated software. Such solutions add greatly to the cost of development and complicate the final design of a DSP.
Therefore, a need has arisen for a simplified method and apparatus for reducing current leakage in a memory using data retention mode.